1. Field of the Invention
The present invention relates generally to a vertical DRAM memory cell and its manufacturing method and, more particularly, to a scalable vertical DRAM cell structure and its manufacturing methods.
2. Description of Related Art
A dynamic random-access-memory (DRAM) cell including an access transistor and a storage capacitor has become the most important storage element in electronic system, especially in computer and communication system. The DRAM density is increased very rapidly in order to decrease the cost per bit and, therefore, an advanced photolithography is in general needed to decrease the minimum-feature-size (F) of a cell.
The output voltage of a DRAM cell is proportional to the capacitance value of the storage capacitor of the DRAM cell and, therefore, the storage capacitor must have a satisfactory capacitance value to have stable operation of the cell as the applied voltage is scaled. Basically, the storage capacitor can be implemented in a trench-type or a stack-type. The trench-type is formed by forming a deep trench in a semiconductor substrate without increasing the surface area of the semiconductor-substrate surface. The stack-type is formed by implementing a capacitor structure over the access transistor and its nearby dummy-transistor structure through the conductive contact-plug over the node diffusion region of the access transistor. Basically, the cell size of the stack-type DRAM is limited by a dummy transistor being formed over the isolation region. Accordingly, the limit cell size of the stack-type DRAM is 8F2 for shallow-trench-isolation. However, the cell size of a trench-type lateral-transistor DRAM is limited by the space between nearby deep-trench capacitors and the separation between the lateral access transistor and the deep-trench capacitor. Therefore, the limit cell size of a trench-type lateral-transistor DRAM is also 8F2 if the separation between the lateral access transistor and the trench capacitor can""t be minimized.
A typical example of a trench-type lateral-transistor DRAM cell is shown in FIG. 1, in which a deep trench is formed in a semiconductor substrate 100. A trench capacitor is formed in a lower portion of the deep trench, in which a lower capacitor node 101 is formed by a heavily-doped n+ diffusion region using an arsenic-silicate-glass (ASG) film as a dopant diffusion source; an upper capacitor node 103a is made of doped polycrystalline-silicon; and a capacitor- dielectric layer 102 is formed by a composite dielectric layer such as an oxide-nitride- oxide structure or a nitride-oxide structure. An oxide collar 104 is used to separate the lower capacitor node 101 from a source diffusion region 105a, 105b, and a capacitor-node connector 103b being made of doped polycrystalline-silicon is used to electrically connect the upper capacitor node 103a to a source conductive node 103c. The source conductive node 103c is made of heavily-doped polycrystalline-silicon to act as a dopant diffusion source for forming an n+ source diffusion region 105a. A shallow-trench-isolation (STI) region 106 is filled with a CVD-oxide layer in order to separate nearby trench capacitors. Two gate- stacks 108, 109 are formed over an upper surface, in which one gate-stack 108 is acted as a passing word-line and another gate-stack 109 being acted as an excess transistor. A common-source diffusion region 105b and a common-drain diffusion region 107 for a bit-line node are formed in an upper surface of the semiconductor substrate 100. From FIG. 1, it is clearly seen that the limit cell size is 8F2 if the space between two nearby trench capacitors is defined to be a minimum-feature-size (F) of technology used. It is clearly seen that the cell size can be further reduced if the separation between two adjacent deep trenches and the common-source region can be reduced.
Apparently, the common-source diffusion region 105b, 105a and the gate-stack 109 shown in FIG. 1 can be removed and are formed in the deep-trench region to become a vertical DRAM cell structure, then the semiconductor surface area can be saved at least 4F2. However, a depth of the deep trenches becomes deeper, resulting in a further problem for forming a deeper trench. Moreover, the threshold-voltage and the punch-through voltage of the vertical transistor are difficult to be controlled, and a longer channel length is therefore used by the prior art. As a consequence, a deeper trench depth is required, and a slower read/write speed of a memory cell due to a longer channel length becomes another serious problem for the prior art.
It is, therefore, a major objective of the present invention to offer a scalable vertical DRAM cell structure for obtaining a scalable cell size of 4F2 or smaller.
It is another objective of the present invention to easily offer different implanted regions for forming punch-through stops and threshold-voltage adjustments of the vertical transistor and the parasitic collar-oxide transistor in a self-aligned manner so a deeper trench is not required.
It is a further objective of the present invention to offer a manufacturing method for forming the scalable vertical DRAM cell structure by using self-aligned techniques with less critical masking photoresist steps.
It is yet another objective of the present invention to offer two different contactless DRAM array structures for high-speed read and write operations.
A scalable vertical DRAM cell structure and its contactless DRAM arrays are disclosed by the present invention. The scalable vertical DRAM cell structure comprises a scalable trench region and a self-aligned common-drain diffusion region of a second conductivity type, in which the scalable trench region comprises a deep-trench region having a vertical transistor and a second-type shallow-trench- isolation region being defined by a first sidewall dielectric spacer and the self-aligned common-drain diffusion region comprises a lightly-doped common-drain diffusion region being formed within a shallow heavily-doped diffusion region. The deep-trench region comprises a lower capacitor node made of an n+ diffusion region being formed in a lower portion of a deep trench, a capacitor-dielectric layer being formed over the lower capacitor node, an upper capacitor node made of a planarized heavily-doped polycrystalline-silicon layer being formed over the capacitor-dielectric layer, a collar-oxide layer being formed over the capacitor-dielectric layer and a portion of the upper capacitor node, a source conductive node integrated with a capacitor-node connector being formed on a portion of the upper capacitor node, a common-source diffusion region being formed by out-diffusion of the source conductive node, an isolation-oxide node being formed over the capacitor-node connector, and a conductive-gate node of a vertical transistor defined by a second sidewall dielectric spacer being formed on the isolation-silicon-dioxide node. The second-type shallow-trench-isolation region being formed outside of the first sidewall dielectric spacer comprises a second-type raised field-oxide layer with a bottom surface level approximately equal to that of the collar-oxide layer and an n+ diffusion region being formed under the second-type raised field-oxide layer. The vertical transistor comprises a capping conductive-gate layer formed outside of a third sidewall dielectric spacer and integrated with the conductive-gate node being defined by a fourth sidewall dielectric spacer, a gate-dielectric layer being formed over a sidewall of the deep trench, a self-aligned common-drain diffusion region being formed over an upper semiconductor surface, and a common-source diffusion region of the second conductivity type being formed near the source conductive node for forming a first-type scalable vertical DRAM cell; and comprises the conductive-gate node being defined by a second sidewall dielectric spacer, a planarized common-gate conductive island integrated with a metal word-line being connected with the conductive-gate node through a common-gate conductive connector island, a gate-dielectric layer being formed over a sidewall of the deep trench, a self-aligned common-drain diffusion region being formed over an upper semiconductor surface, and a common-source diffusion region being formed near the source conductive node for forming a second-type scalable vertical DRAM cell. The self-aligned common-drain region comprises a shallow heavily-doped common-drain diffusion region formed within a lightly-doped common-drain diffusion region and said semiconductor substrate under said self-aligned common-drain diffusion region comprises a deep implant region of the first conductivity type being formed near a middle portion outside of said gate-dielectric layer and a deeper implant region of the first conductivity type being formed near a middle portion outside of said collar-oxide layer. A planarized common-drain conductive island integrated with a metal bit-line being formed on the shallow heavily-doped common-drain diffusion region outside of a fifth sidewall dielectric spacer being formed over a sidewall of the deep-trench region for forming the first-type scalable vertical DRAM cell; and a common-drain conductive bit-line being formed over the shallow heavidly-doped common-drain diffusion region and two first-type fourth raised field-oxide layers outside of a fifth sidewall dielectric spacer being formed over a sidewall of the deep-trench region for forming the second-type scalable vertical DRAM cell. The cell size of the scalable vertical DRAM cell structure is scalable and can be fabricated to be equal to or smaller than 4F2.
The scalable vertical DRAM cell structure of the present invention is used to implement two contactless DRAM arrays. A first-type contactless DRAM array comprises a plurality of first-type scalable vertical DRAM cells, a plurality of metal bit-lines integrated with the planarized common-drain conductive islands being patterned to be aligned above a plurality of active regions, and a plurality of capping conductive-gate layers integrated with the conductive-gate nodes to act as a plurality of conductive word-lines being formed transversely to the plurality of metal bit-lines. A second-type contactless DRAM array comprises a plurality of second-type scalable vertical DRAM cells, a plurality of metal word-lines integrated with planarized common-gate conductive islands over common-gate conductive connector islands being patterned to be aligned above a plurality of active regions, and a plurality of highly conductive common-drain bus-lines acted as a plurality of conductive bit-lines being formed transversely to the plurality of metal word-lines.